Master degree in microelectronics, electronic engineering, communication or related fields; 微电子、电子工程、通信或相关专业研究生;
Knowledge in ASIC RTL design and verification at the chip level and block level； 具有芯片级和模块级ASIC RTL设计和验证知识；
Strong Verilog, system Verilog, UVM, PERL, and TCL skills； 熟悉Verilog，system Verilog, UVM, PERL和TCL技能
Knowledge in silicon debugging
了解芯片测试功能
Demonstrates good communication skills in both Mandarin and English
良好的沟通能力
Demonstrates good analysis and problem-solving skills
良好的分析和解决问题的能力
Knowledge of high speed interface protocols is a plus
具备高速接口协议知识优先
Working as part of a highly experienced IP design team, the candidate will be involved in designing and maintaining current and next generation, related products are Interface Controller/High-speed DDR PHY /Serdes/ Static Memory/Processor using advanced design process (such as 5nm/7nm/10nm), etc;
